The present invention relates to a semiconductor integrated circuit comprised of a plurality of transistors in combination, and more particularly, it relates to an improved technology for reduced power consumption and accelerated signal transmission rate.
To attain acceleration of a reduced power consumption complementary metal oxide semiconductor (CMOS) logic circuit, it is required that the circuit is comprised of low threshold voltage transistors. However, there arises a problem that as a threshold voltage in the transistors is reduced, leak current during standby state is increased.
An improved multiple threshold voltage CMOS circuit (MT-CMOS circuit) has been proposed which effectively avoids this problem and is capable of attaining accelerated circuit operation and reduced leak current during standby state simultaneously.
FIG. 10 is a circuit diagram showing the prior art MT-CMOS circuit. The circuit in FIG. 10 is comprised of a virtual power supply line VDD1 connected to a power supply line VDD with an intervening high threshold voltage transistor Q1, and a virtual ground line VSS1 connected to a ground line VSS with an intervening low threshold voltage transistor Q2.
A low-Vth block 100, which has low threshold voltage transistors, is connected between the virtual power supply line VDD1 and the virtual ground line VSS1.
The low-Vth block 100 functions as an OR circuit, for example, and includes two P channel MOS transistors Q3 and Q4 which receive input signals IN1 and IN2 from respective gate electrodes thereof, and are connected in parallel between the virtual power supply line VDD1 and a node N, and two N channel MOS transistors Q5 and Q6 which similarly receive input signals IN1 and IN2 from respective gate electrodes thereof and are connected in series between the virtual power supply line VSS1 and the node N. Also, connected to the node N is an inverter comprised of a P channel transistor Q7 and an N channel transistor Q8 connected in series and having their respective gates connected to the node N in common.
Operation of the circuit will be detailed below.
During an operation (when the circuit is activated), both the transistors Q1 and Q2 are turned on to supply the low-Vth block 100 with supply voltage. The low-Vth block 100 operates at high speed since it is comprised of low threshold voltage transistors.
On the contrary, during a standby state, both the transistors Q1 and Q2 are turned off to break a leak path from the power supply line VDD to the ground line VSS, and hence, leak current is reduced.
In such a method, however, amounts of current supplied during the operation from the power supply line VDD to the virtual power supply line VDD1 and from the virtual ground line VSS1 to the ground line VSS depend upon a resistance (ON-resistance) at the activated high threshold voltage transistors Q1 and Q2. Thus, the ON-resistance should be reduced to attain an acceleration of the operation. For that purpose, it is required to enlarge gate widths of the high threshold voltage transistors Q1 and Q2, and this leads to an adverse effect of an increase in a chip area.
According to an embodiment of the present invention, there is provided a semiconductor integrated circuit, comprising:
a first reference voltage line;
a second reference voltage line;
a plurality of single logic circuits each including a plurality of transistors;
a first switch having a first transistor provided between said first reference voltage line and said logic circuits, said first transistor having a higher threshold voltage than that of transistors in the logic circuits; and
a second switch having a second transistor provided a between said second transistor having a higher threshold voltage than that of transistors in the logic circuits,
said first and second switches being turned on when at least one of said single logic circuits is in operation, while said first and second switches being turned off when all of said single logic circuits are in standby state.
According to further embodiment of the present invention, there is provided a semiconductor integrated circuit, comprising:
a first reference voltage line;
a second reference voltage line;
a plurality of single logic circuits each comprised of combined transistors having first and second virtual power supply lines;
a first shared switch interposed between said first reference voltage line and said first virtual power supply line for the single logic circuits, the first shared switch being a transistor having higher threshold voltage than that of the transistors of said single logic circuits; and
a second shared switch interposed between the second reference voltage line and the second virtual power supply line for the single logic circuits, the second shared switch being a transistor having higher threshold voltage than that of the transistors of said single logic circuits;
said first and second shared switches being turned on when at least one of said single logic circuits is in operation, while said first and second shared switches being turned off when all of said single logic circuits are in standby state.
According to still further embodiment of the present invention, there is provided a semiconductor integrated circuit, comprising:
a first reference voltage line;
a second reference voltage line;
a plurality of single logic circuits each comprised of transistors having first and second virtual power supply lines;
a first shared switch interposed between the first reference voltage line and the first virtual power supply line for the single logic circuits, the first shared switch being a transistor higher in threshold voltage than the transistors of the single logic circuits; and
a second shared switch interposed between the second reference voltage line and the second virtual power supply line for the single logic circuits, the second shared switch being a transistor higher in threshold voltage than the transistors of the single logic circuits,
said at least one of the single logic circuits is in a transition state, no transition of the output voltage being developed in the remaining single logic circuits.
According to further embodiment of the present invention, there is provided a semiconductor integrated circuit, comprising:
a first reference voltage line;
a second reference voltage line;
a plurality of single logic circuits each comprised of transistors in combination having first and second virtual power supply lines, the single logic circuits being segmented into three or more groups;
a first shared switch interposed between the first reference voltage line and the first virtual power supply line for the single logic circuits in odd-numbered segments, the first shared switch being a transistor higher in threshold voltage than the transistors of the single logic circuits; and
a second shared switch interposed between the second reference voltage line and the second virtual power supply line for the single logic circuits in the odd-numbered segments, the second shared switch being a transistor higher in threshold voltage than the transistors of the single logic circuits,
the single logic circuits in even numbered segments being capable of delaying transition of output voltage so that output voltages from the single logic circuits in the odd numbered segments would not simultaneously be in a sate of transition.